伪通孔对铜互连应力诱生空洞的影响  

Effect of Dummy Via on Stress Induced Voiding in Copper Interconnect

作　　者：侯通贤[1,2] 姚若河[1] 林晓玲[1,2] 

机构地区：[1]华南理工大学电子与信息学院,广州510640 [2]电子元器件可靠性物理及其应用技术国家重点实验室,广州510610

出　　处：《微电子学》2010年第2期295-299,共5页Microelectronics

基　　金：电子元器件可靠性物理及其应用技术国家重点实验室基金资助项目(9140C03010408DZ15)

摘　　要：基于铜的随动强化模型,使用三维有限元方法,分析在窄-宽线铜互连结构中添加伪通孔对互连应力诱生空洞的影响。对宽互连M1分别为无伪通孔、中间添加伪通孔、右侧边沿添加伪通孔和添加双伪通孔结构进行了研究。结果表明,添加伪通孔不但可以降低通孔底部互连M1区域的空洞生长速率,而且使伪通孔正下面的互连M1成为额外的空位收集器,从而有效地提高互连应力诱生空洞性能,双伪通孔可进一步增强应力诱生空洞性能。Based on copper kinematic hardening model, effect of dummy via on stress-induced voiding （SIV） in narrow-wide copper interconnect structure was analyzed by using three-dimensional finite element method. For wide M1 interconnect, structures of no dummy via, dummy via in the middle, dummy via in the edge of right side and double dummy vias were investigated, respectively. Simulation results showed that dummy via not only reduced void growth rate on via bottom of M1 interconnect, but also turned M1 interconnect under the dummy via into additional vacancy collector, thus effectively reducing SIV. It is concluded that double dummy vias could further enhance SlV performance.

关 键 词：伪通孔 铜互连 应力诱生空洞 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]