10Gb/s 0.35μm SiGe BiCMOS伪差分共基极输入前端放大电路的设计  

Design of a 10Gb/s 0.35μm SiGe BiCMoS front-end amplifier using a pseudo-difierential common-base input stage

作　　者：陈准[1] 冯军[1] 王远卓[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《高技术通讯》2010年第7期750-753,共4页Chinese High Technology Letters

基　　金：863计划(2006AA01Z284)资助项目

摘　　要：采用Jazz 0.35μm SiGe BiCMOS工艺设计实现了应用于10Gb/s速率级光接收机的前端放大电路。该电路由前置放大器与限幅放大器构成,两者均采用了差分电路形式。前置放大器由共基输入级和带并联负反馈的放大器组成。跨导放大器中的基本放大器采用共集-共发-共基的组合结构扩展带宽。限幅放大器采用两级Cherry-Hooper结构。芯片面积仅为0.47mm^2。测试结果表明,在3.3V的供电电压下,总功耗为158mW。在输入电压信号25mV时,可以得到清晰对称的眼图。A 10Gb/s front-end amplifier for optical receivers was realized in a 0.35μm SiGe BiCMOS technology. It combines a preamplifier and a limiting amplifier and both of them are realized with the differential architecture. The preamplifier consists of a common base input stage and a parallel negative feedback amplifier. The common-collector-common-emittercommon-base configuration is used to expand the bandwidth of basic amplifiers in transconductance amplifiers. The limiting amplifier consists two stages of Cherry-Hooper architecture. The chip die area is only 0.47mm^2. The measurement result shows that the total power dissipation is 158mW with the supply voltage of 3.3V. With a 25mV input signal a clear and symmetric eye-diagram can be obtained.

关 键 词：光纤通信 前置放大器 限幅放大器 Cherry-Hooper结构 0.35μm SIGE BICMOS工艺 共基极 

分 类 号：TN721[电子电信—电路与系统]