数字逻辑实验教学改革探索  

Exploration of Experiment Teaching of Digital Logic

作　　者：盛建伦[1] 

机构地区：[1]青岛理工大学计算机学院,山东青岛266033

出　　处：《计算机教育》2010年第17期41-43,共3页Computer Education

摘　　要：针对数字逻辑实验教学存在的问题,提出数字逻辑课程实验教学改革和实验课题设计的思想,改传统的验证性实验为用VHDL语言做设计性实验;介绍实验课题的设计和教学效果。实验课题应该是课程的主要知识点,有合适的难度,无现成的答案。实验课题包括两个组合逻辑设计和3个时序逻辑设计课题,有基本实验,还有选做题目。教学效果表明实验课题的设计是成功的,达到了预期的目的。Aimed at the problems in experiment teaching of digital logic, the idea of reforming experiment teaching of digital logic and designing experiment task is proposed in this paper. The traditional test-and-verify experiments are replaced with design experiments of VHDL. The design of experiment tasks and the teaching effect are introduced. The experiment tasks should be the major point of knowledge and in appropriate difficulty and no existing answer. The experiment tasks include two combinational logic design and three sequential logic design tasks. There are basic experiments and optional experiments as well. The teaching effect shows that the design of experiment tasks is successful, and the anticipating aim is achieved.

关 键 词：数字逻辑 实验教学 实验课题设计 教学改革 VHDL 

分 类 号：G642[文化科学—高等教育学]