RF LDMOS功率器件研制  

Design and Fabrication of RF Power LDMOS

作　　者：陈蕾[1] 王帅[1] 姜一波[1] 李科[1] 杜寰[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2010年第10期968-972,共5页Semiconductor Technology

摘　　要：基于ISE TCAD模拟软件对RF LDMOS器件的工艺流程和器件结构进行了优化设计,采用带栅极金属总线的版图结构降低栅电阻,同时简化了LDMOS器件的封装设计。通过实际流片和测试分析,重点讨论了漂移区注入剂量和漂移区长度对LDMOS器件的转移特性、击穿特性、截止频率及最大振荡频率的影响。测试结果表明该器件的阈值电压为1.8 V,击穿电压可达70 V,截止频率和最大振荡频率分别为9 GHz和12.6 GHz,并可提供0.7 W/mm的输出功率密度。Using ISE TCAD simulation soft,the process flow and structure of RF power LDMOS were optimized.By the layout design of gate bus structure,the gate resistance was reduced and the package design of LDMOS was also simplified.Through the wafer fabrication and test,the influences of drift region doping dose,drift region length on LDMOS threshold voltage,breakdown voltage and frequency character were discussed.The results show that the breakdown voltage is 70 V,and threshold voltage is 1.8 V.The cutoff frequency is 9 GHz and max oscillator frequency is 12.6 GHz.About 0.7 W/mm output power density can be provided.

关 键 词：射频LDMOS功率器件 击穿电压 栅极金属总线 截止频率 最大振荡频率 

分 类 号：TN386.1[电子电信—物理电子学]