一种基于FPGA的新的SVM硬件实现方法  

New serial implementation method for support vector machines using FPGA

作　　者：刘涵[1] 王博[1] 尹嵩[1] 刘丁[1] 

机构地区：[1]西安理工大学自动化与信息工程学院,西安710048

出　　处：《仪器仪表学报》2010年第10期2235-2241,共7页Chinese Journal of Scientific Instrument

基　　金：陕西省教育厅专项基金(09JK632)资助项目

摘　　要：提出了一种基于递归神经网络的实现最小二乘支持向量机的FPGA串行计算方法,与已有的并行计算方法相比,该方法利用了递归神经网络的并行性及最小二乘支持向量机简化的约束条件的优点,在保证计算速度的同时,明显提高了FPGA的硬件资源利用效率,能够适应大规模训练样本的情况。实验结果表明,由于该方法具有灵活的串行计算、并行传输的特点,在较少使用FPGA硬件资源的同时,计算速度不会有明显变化,可有效地用硬件实现支持向量机。A new FPGA serial computational method for implementing least squares support vector machines based on recurrent neural network is presented in this paper. Compared with existing parallel computational method, the new method combines the parallel character of recurrent neural network with simplicity of least squares support vector machine, can get a good performance with less hardware resources while maintaining the computational speed, and also can adapt to large-scale training samples. Experiment results show that due to the flexible serial computational and parallel transmission characteristics, the consumption of FPGA space could be reduced effectively while the computing speed will not drop obviously. In conclusion, the function of support vector machines could be implemented on FPGA platform using the proposed method effectively.

关 键 词：串行计算方法 最小二乘支持向量机 递归神经网络 

分 类 号：TN911.7[电子电信—通信与信息系统]