VDMOS均匀掺杂外延区优化设计的简单理论  

Simple Theory of Optimum Design of the Epitaxial Layers with the Uniform Doping for VDMOS Transistor

作　　者：何进[1] 陈星弼[1] 王新[1] 

机构地区：[1]电子科技大学微电子所,成都610054

出　　处：《电子器件》1999年第3期143-148,共6页Chinese Journal of Electron Devices

基　　金：国家自然科学基金

摘　　要：在高压ＶＤＭＯＳ器件中，保证足够高的漏源击穿电压ＢＶＰＴ和尽可能低的比导通电阻Ｒｏｎ是设计中必须同时考虑的两个相互矛盾的主要方面。对于耐压高的ＶＤＭＯＳ，Ｒｏｎ主要由外延区决定。本文通过外延区为均匀掺杂的ＶＤＭＯＳ穿通击穿条件和外延区比导通电阻Ｒｏｎ的理论分析，首次得到了Ｒｏｎ随外延区参数、击穿电压变化的简捷普适关系。在此基础上提出了ＶＤＭＯＳ为均匀掺杂外延区时优化设计的简单理论：对于各种高压ＶＤＭＯＳ，只要外延区厚度取为同衬底浓度下突变结击穿时耗尽层宽度的最佳分割长度，即利用系数η０＝ ０．７５，就可保证外延区Ｒｏｎ 为最小。凭借此理论，可以用熟知的突变结击穿参数计算ＶＤＭＯＳ外延区优化参数，而且结果与其它文献的理论计算相吻合，二者相差不大于３％ 。这一理论结果可直接作为功率ＭＯＳ等非电导调制器件的设计准则。The dominant feature of high voltage VDMOSFET design is the trade off between the ideal breakdown voltage and the ideal on resistance R \-\{on\}. On the basis of analysis of the punch through breakdown and the minimization of R \-\{on\} conditions of VDMOS with the uniform doping epitaxial layers, the common expressing of R \-\{on\} is found and the simple theory of optimization of the uniform doping epitaxial layers of VDMOS has been developed. The minimization of R \-\{on\} can be achieved by seting the epitaxial thickness W \-\{PT\} to be η \-0 W \-\{PN\},which η \-0 is equal to 0.75 (the best design coefficient), which W \-\{PN\} is the depletion width of Abrupt junctions with the same substrate concentrations at breakdown. By the means of the above theory results, the optimum parameters of epitaxial layers for VDMOS can be obtained by the known abrupt junctions breakdown parameters, and the results is well conincide with the ones by the given theory of the literature [10] .

关 键 词：VDMOS 外延区优化 掺杂 场效应晶体管 设计 

分 类 号：TN386.053[电子电信—物理电子学] TN386.02