VDMOS均匀掺杂外延区的优化设计  

Optimum Design of Epitaxial Layers With Uniform Doping for VDMOS Transistor

作　　者：何进[1] 王新[1] 陈星弼[1] 

机构地区：[1]电子科技大学微电子所,成都610054

出　　处：《Journal of Semiconductors》1999年第11期977-982,共6页半导体学报（英文版）

基　　金：国家自然科学基金

摘　　要：本文通过外延区为均匀掺杂的ＶＤＭＯＳ穿通击穿条件和外延区比导通电阻Ｒｏｎ的理论分析，首次得到了Ｒｏｎ随外延区参数、击穿电压变化的简捷普遍关系式．在此基础上提出了ＶＤＭＯＳ为均匀掺杂外延区时的优化设计理论：对于各种高压ＶＤＭＯＳ，只要外延区厚度取为同衬底浓度下突变结击穿时耗尽层宽度的最佳分割长度，即穿通因数Ｆ的倒数η为０７５ 时，就可保证外延区Ｒｏｎ为最小．凭借此理论，本文首次推出了ＶＤＭＯＳ外延区优化设计的严格理论公式，纠正了一些文献引用经验关系或突变结关系导出的设计公式的不准确性及错误结论．这些理论结果可直接作为功率ＭＯＳ等非电导调制器件的设计准则．The dominant feature of high\|voltage VDMOSFET design is the trade off between the ideal breakdown voltage and the ideal on\|resistance R on .On the basis of analysis of the punch\|through breakdown and the minimization of R on conditions of VDMOS with the uniform doping epitaxial layers,the common expressing of R on is found and the theory of optimization of the uniform doping epitaxial layers of VDMOS has been developed. The minimization of R on can be achieved by setting the epitaxial thickness W PT to be η\-0 W \{PN\}, η 0 being equal to 0 75(the best design coefficient), W PN being the depletion width of abrupt junctions with the same substrate concentrations at breakdown. By means of the theory results mentioned above, the optimum parameters expression of epitaxial layers for VDMOS have also been obtainned, which can directly be used in optimum design of the non\|conductivity modulation power semiconductor devices.

关 键 词：VDMOS 场效应晶体管 掺杂 外延区 优化设计 

分 类 号：TN386.602[电子电信—物理电子学]