基于Verilog语言的边界扫描结构设计  

Design Method of Boundary-scan Circuit Architecture Based on Verilog Language

作　　者：陈圣俭[1] 周银[1] 徐磊[1] 周浔[1] 王蒙蒙[1] 

机构地区：[1]装甲兵工程学院控制工程系

出　　处：《装甲兵工程学院学报》2011年第2期50-54,共5页Journal of Academy of Armored Force Engineering

基　　金：国家自然科学基金资助项目(60871029)

摘　　要：以对74290IP核加载边界扫描结构为例,采用硬件描述语言Verilog对边界扫描结构进行了模块化设计,并进行了边界扫描测试仿真。结果表明：加载边界扫描结构后的核心逻辑能够实现功能内测试和外部互联测试。该设计方法简单可行,具有一定的通用性,为智能BIT设计、装备健康管理设计中的底层数据采集提供了技术支撑。A general design method which loads the boundary-scan architecture into the logic core of circuit is proposed.Taking the IP core of 74290 as an example,the modular design of boundary-scan architecture is described by Verilog language,and the corresponding boundary-scan tests is emulated.The simulation and experiment results prove that the method is correct and feasible.The IP core with boundary-scan circuit architecture can achieve testing of the system logic and board level interconnections.

关 键 词：边界扫描 VERILOG IP核 可测性设计 

分 类 号：TP331.1[自动化与计算机技术—计算机系统结构]