循环冗余校验算法的FPGA高速实现  

Implementation of cyclic redundancy check algorithm using FPGA with high speed

作　　者：耿文波[1] 张思维[2] 

机构地区：[1]周口师范学院物理与电子工程系,河南周口466001 [2]黄淮学院电子科学与工程系,河南驻马店463000

出　　处：《周口师范学院学报》2011年第5期32-35,共4页Journal of Zhoukou Normal University

基　　金：周口师范学院青年科研基金资助项目(No.ZKNUQN201042A)

摘　　要：介绍了循环冗余校验原理,并以CRC-16生成多项式为例,用Verilog HDL硬件描述语言描述该算法.采用Quartus Ⅱ 8.0进行综合、仿真,并用Cyclone Ⅱ系列的EP2C35F672C6器件适配和编程下载,在DE2开发板上实现.该CRC模块既是CRC校验生成模块,又是CRC校验检错模块.另外,该CRC模块还可以封装成具有Avalon总线接口的自定义组件IP核,从而可以重复利用.实验结果表明,该校验器速度快,占用资源少,并在实际中得到了应用.Cyclic Redundancy Check （CRC） is a type of channel coding technology used for error detection and control in digital communication. After introducing the principle of CRC, taking CRC - 16 polynomial as an example, the author described the CRC algorithm using hardware description language Verilog HDL. CRC module is synthesized, fitted and simulated by Quartus Ⅱ 8.0, programmed into the Cyclone II family device EP2C35F672C6 and implemented on DE2 board. The module is the combination of CRC generator and CRC checker. In addition to, this CRC module can be packed as a custom component with Avalon - MM interface and be shared with other designer. The result of the experiment showed that this CRC module has a high speed, less resources consumption, and it is used in actual application.

关 键 词：循环冗余校验 生成多项式 VERILOG HDL语言 现场可编程门阵列 

分 类 号：TN914.3[电子电信—通信与信息系统]