Universal trench design method for a high-voltage SOI trench LDMOS  

作　　者：胡夏融 张波 罗小蓉 李肇基 

机构地区：[1]State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China

出　　处：《Journal of Semiconductors》2012年第7期47-50,共4页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(Nos.61176069,60976060);the National Key Laboratory of Analogue Integrated Circuit,China(No.9140C090304110C0905)

摘　　要：The design method for a high-voltage SOI trench LDMOS for various trench permittivities, widths and depths is introduced. A universal method for efficient design is presented for the first time, taking the trade-off between breakdown voltage （BV） and specific on-resistance （Rs, on） into account. The high-k （relative permittivity） dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench. An SOI LDMOS with a vacuum trench in the drift region is also discussed. Simulation results show that the high FOM BV2/Rs, on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.The design method for a high-voltage SOI trench LDMOS for various trench permittivities, widths and depths is introduced. A universal method for efficient design is presented for the first time, taking the trade-off between breakdown voltage （BV） and specific on-resistance （Rs, on） into account. The high-k （relative permittivity） dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench. An SOI LDMOS with a vacuum trench in the drift region is also discussed. Simulation results show that the high FOM BV2/Rs, on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.

关 键 词：SOI TRENCH PERMITTIVITY RESURF LDMOS breakdown voltage 

分 类 号：TN386[电子电信—物理电子学]