nMOSFET中衬底偏压对衬底电流的影响研究  

Effect of Substrate Bias on Substrate Current in nMOSFET

作　　者：陈海峰[1] 过立新[1] 

机构地区：[1]西安邮电大学电子工程学院,西安710121

出　　处：《微电子学》2013年第1期103-106,共4页Microelectronics

基　　金：陕西省教育厅专项科研基金资助项目(11JK0902);西安市应用材料创新基金资助项目(XA-AM-201012)

摘　　要：研究了基于90nm CMOS工艺的nMOSFET中正负衬底偏压VB对衬底电流IB的影响。衬底电流IB在0V<VG<1V时变化比较明显,IB随VB正偏压的增加而增大,随VB负偏压的增加而减小。这是因为在这一区间内对IB起主导作用的漏电流ID主要为亚阈值电流,而VB对与亚阈值电流紧密相关的阈值电压VTH会产生较大影响。进一步研究发现,衬底电流峰值IBMAX与VB在半对数坐标下呈线性关系。实验结果验证了VB对IB的这一影响机制在不同VD下的普适性。给出了相关的物理机制。Effects of substrate bias VB on substrate current IB in 90 nm nMOSFET were studied.IB changed significantly for 0 VVG1 V,and IB increased with increasing positive VB and decreased with increasing negative VB.This was ascribed to the fact that VB had great effect on threshold voltage VTH,which was closely related to sub-threshold current,while drain current ID,which dominated IB in this VG region,mainly came from sub-threshold current.Moreover,the peak substrate current IBMAX varied linearly with VB in semi-logarithmic coordinates.This mechanism of VB effect on IB was validated for different VD,and related physical mechanism was presented.

关 键 词：衬底电流 亚阈值电流 NMOSFET 衬底偏压 

分 类 号：TN386.1[电子电信—物理电子学]