一种适于GNSS信号快捕的FFT核的设计与实现  

Design and Implement of FFT Core Applying to the Fast Acquisition of GNSS Signal

作　　者：汤震武[1] 盛利元[1] 杨俊[2] 

机构地区：[1]中南大学物理与电子学院,湖南长沙410083 [2]国防科技大学机电工程与自动化学院,湖南长沙410073

出　　处：《宇航计测技术》2013年第3期28-33,共6页Journal of Astronautic Metrology and Measurement

摘　　要：针对GNSS信号捕获的要求,在Quartus II 7.2集成开发环境下,采用Verilog HDL语言,设计了一种256点复数基2时间抽取FFT处理器。利用Matlab工具联合Quartus II进行仿真,提高仿真效率,并最后进行硬件测试。结果表明,本文设计的FFT处理器具有较小的面积和较高的处理速度,能够满足GNSS接收机信号处理的要求。With the requirements of fast acquisition of GNSS signal, a FYT processor of radix-2 with 256 points complex input is designed in this paper. The FFT core was designed with Verilog HDL language under the Quartus II 7.2, and in order to improve the simulation efficiency, Matlab is used to simulate together with Quartus. Finally a test was done on the design and the result shows that the FFT processor designed in the paper has less resource consumption and higher processing speed, meeting the basic requirement of GNSS receivers.

关 键 词：快速傅里叶变换 现场可编程门阵列 联合仿真 VERILOG HDL语言 

分 类 号：TN911.72[电子电信—通信与信息系统]