基于MARCH算法的SRAM内建自测试设计  

Design of BIST Testing SRAM Based on MARCH Algorithm

作　　者：张铜[1] 成本茂[1] 张小锋[1] 

机构地区：[1]南昌航空大学信息与工程学院,江西南昌330063

出　　处：《计算机与现代化》2013年第8期99-101,共3页Computer and Modernization

摘　　要：随着FPGA集成度和复杂性的增加,测试显得尤为重要,但是测试是FPGA设计中费用最高、难度最大的一个环节。由于片上系统的快速发展,ATE的速度及其存储量已经不能满足测试的要求,因此出现了内建自测试技术。本研究的主要目的是实现一个对32个单元、每个单元8比特大小的SRAM测试的BIST,采用的测试方法为MARCH算法。在设计中采用的是Verilog语言,用QautusⅡ9.0软件对设计进行仿真,并对仿真结果进行分析判断。With the development of complexity and integration of FPGA, the test technology becomes more important. But the test costs the highest in the design and is the most difficult. As the rapid development of the System-on-Chip, the rate of ATE and memory space of ATE can not satisfy the requirements of the test, so the Built-In-Self-Test method appeared in this world. The purpose of design is to achieve a BIST machine to test a SRAM of 32 words eaeh of 8-bits. The algorithm to be used for BIST is MARCH algorithm. The design should be implemented in Verilog, simulated using Qautus Ⅱ9.0.

关 键 词：内建自测试 MARCH算法 QautusⅡ9 0 

分 类 号：TP206[自动化与计算机技术—检测技术与自动化装置]