确定性测试矢量生成的低功耗设计  

Low Power Design by Determinstic Test Vectors Generation

作　　者：李鹏[1] 颜学龙[1] 孙元[1] 

机构地区：[1]桂林电子科技大学电子工程与自动化学院,广西桂林541004

出　　处：《电子器件》2013年第5期612-617,共6页Chinese Journal of Electron Devices

摘　　要：在组合电路内建自测试过程中,为了保证在获得较高故障覆盖率的条件下,减少测试功耗,提出了一种确定性低功耗测试矢量的生成结构,该结构利用可配置反馈网络的LFSR作为确定性矢量生成器,并结合单翻转矢量插入逻辑的时钟复用原理,使确定性测试矢量间插入了单一跳变的测试矢量。通过对组合电路集ISCAS’85的实验,表明该设计不仅提高了故障覆盖率,缩短了测试时间,而且能有效降低电路的总功耗、平均功耗和峰值功耗。In the process of testing combinational circuit using BIST method,a determinstic test vectors with low power consumption generation structure is presented,which decreases the test power consumption in the circumstances of ensuring the higher stuck-at fault coverage. The proposed method uses a structure of configurable LFSR to generate the deterministic test vectors and combines the theory of single switching activities logic with operating in different clock to achieve the single switching vectors between each determinstic vectors. According to experimenting in ISCAS＇85,the proposed scheme verifies not only to improve the fault coverage but also shorten the test time and effectively reduce the total power consumption,average power consumption and peak power consumption in CUT.

关 键 词：内建自测试 故障覆盖率 确定性测试矢量 测试功耗 可配置LFSR 

分 类 号：TN402[电子电信—微电子学与固体电子学]