8Transistors SRAM稳定性分析与验证  

Analysis and Verification of Stability for 8Transistors SRAM

作　　者：丁艳[1] 刘章发[1] 

机构地区：[1]北京交通大学电子信息工程学院,北京100044

出　　处：《微处理机》2013年第2期1-5,共5页Microprocessors

摘　　要：针对8transistors(8T)静态随机存储器(SRAM)存储单元的基本结构,详细研究分析了影响存储单元稳定性性能的因素。为了提升SRAM的稳定性和控制SRAM面积,提出了一种提升稳定性的同时又能有效控制芯片面积的技术方案。在SMIC 40nm工艺条件下,验证了该技术方案,实现了预期的目标,其中稳定性大约提升10%左右。In this paper,a detailed analysis of factors affecting the stability of the performance of bitcell was presented for the basic structure of the 8transistors（8T） static random access memory（SRAM） cell.In order to enhance the stability of the SRAM and reduce the area of the SRAM,a technical solution was proposed in this paper.The technical solution was verified in SMIC 40nm process and the desired objectives were obtained.Especially,the stability performance has been improved about 10%.

关 键 词：静态存储器 稳定性 预充电 噪声容限 写容限 读电流 

分 类 号：TN453[电子电信—微电子学与固体电子学]