3GHz高速ADC陶瓷封装的电学设计  

Electrical Design of Ceramic Package for 3 GHz High Speed ADC

作　　者：张洪硕[1] 赵元富[1] 姚全斌[1] 曹玉生[1,2] 练滨浩[1] 朱国良[1] 

机构地区：[1]北京微电子技术研究所,北京100076 [2]北京时代民芯科技有限公司,北京100076

出　　处：《半导体技术》2014年第3期214-219,共6页Semiconductor Technology

基　　金：国家科技重大专项资助项目(2011ZX02607)

摘　　要：随着模数转换器(ADC)采样频率的提高,保证其电压采样精度成为封装设计中的难题。完成了一款采样频率为3 GHz的ADC陶瓷外壳的设计,根据设计规则及EDA软件仿真结果,确定ADC外壳的层叠结构及走线,使阻抗有较好的匹配性,降低信号反射;使用全波电磁场分析软件对不同材料、不同直径键合丝的传输特性进行了仿真,对关键信号放置在不同层情况下的插入损耗进行分析对比,选择符合工艺条件的最优方案。仿真结果表明该设计达到了3 GHz ADC的外壳设计要求,但实际测试结果与仿真结果有一定误差,测试用印刷电路板(PCB)的插入损耗可能是导致差异的一个重要原因。With the increase of analog-to-digital converters （ADC） sampling frequency, it is difficult for the package design to guarantee the voltage accuracy of the sample. An ADC ceramic package with sampling frequency of 3 GHz was designed. According to the design rules and simulation results of EDA, the cascade structure and line of ADC package were confirmed, the impedance was well matched, and the reflection of the signal was reduced. By the full wave analysis software, the bonding wire transmission performances of different material and diameter were simulated. The insertion loss of the key signal in different layer is analyzed and compared. Based on the analysis, the best scheme which complies with process requirements can be chose. The results show that this package design can meet the requirement of the 3 GHz ADC, but there is error between the simulation results and the test results, the insertion loss of the printed circuit board （PCB） may be the main reason that leads this error.

关 键 词：陶瓷封装 电学设计 传输特性 插入损耗 模数转换器(ADC) 

分 类 号：TN305.94[电子电信—物理电子学] TN402