TDDB characteristic and breakdown mechanism of ultra-thin SiO_2/HfO_2 bilayer gate dielectrics  

作　　者：陶芬芬 杨红 唐波 唐兆云 徐烨锋 许静 王卿璞 闫江 

机构地区：[1]School of Physics,Shandong University [2]Key Laboratory of Microelectronics Devices and Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2014年第6期32-37,共6页半导体学报（英文版）

基　　金：Project supported by the Important National Science & Technology Specific Projects(No.2009ZX02035);the National Natural Science of China(No.61306129);the National Found for Fostering Talents of Basic Science(No.J0730318)

摘　　要：The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.

关 键 词：HFO2 TDDB SILC bulk trap interface trap 

分 类 号：TN386[电子电信—物理电子学]