低压VDMOSFET导通电阻的优化设计  

Optimal Design of On-state Resistance for Low-voltage VDMOS

作　　者：赵野[1] 张颖[1] 高嵩[1] 石广元[1] 

机构地区：[1]辽宁大学物理系,辽宁沈阳110036

出　　处：《辽宁大学学报（自然科学版）》2001年第3期247-252,共6页Journal of Liaoning University：Natural Sciences Edition

摘　　要：对低压VDMOSFET导通电阻Ron的各个构成部分进行了理论分析 ,较为详细地讨论了窗口区和多晶硅栅区的尺寸和比例对器件的导通电阻的影响 .通过这些分析和计算 ,得出了VDMOSFET单元设计的最佳原则 ,并给出了低压条件下最佳单元尺寸 .The theoretical analysis on every component of on state resistance to low voltage is presented. The effects of on state resistance of devices on scaled design of dimensions of windows and poly silicon gate are discussed in details. After analysis and calculation, optimal principle on VDMOSFET cell design is obtained. At the same time, optimal cell dimensions of low voltage are also given.

关 键 词：单胞尺寸 特征电阻 VDMOSFET 优化设计 集成电路 导通电阻 

分 类 号：TN386.1[电子电信—物理电子学] TN323.4