基于加速退化试验的模拟IC寿命评估研究  

Lifetime Assessment of Analog IC based on Accelerated Degradation Test

作　　者：罗俊[1,2] 王健安[1] 郝跃[2] 代天君[1] 晏开华[1] 李金龙[1] 黄姣英[3] 

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060 [2]西安电子科技大学微电子学院宽禁带半导体材料与器件重点实验室,西安710071 [3]北京航空航天大学可靠性与系统工程学院,北京100191

出　　处：《微电子学》2014年第4期523-526,共4页Microelectronics

摘　　要：为解决高可靠性、长寿命模拟集成电路的寿命评估问题,结合半导体器件退化失效的特点,提出了基于加速退化试验的模拟集成电路寿命评估方法。在此基础上,以某型电压基准模拟IC为研究对象,通过对退化数据的分析研究,获得了其在正常工作应力下的寿命数据。For high reliability semiconductor analog ICs, it is difficult to assess the lifetime by using traditional reliability analysis method since no enough failure data can be obtained in a short duration. Aiming at this problem, a new lifetime estimation method is proposed for analog ICs based on accelerated test degradation test according to the characteristics of semiconductor devices degradation failure. Degradation data of a certain type of voltage reference analog IC is analyzed, and the estimated lifetime value under actual working condition is obtained by this approach.

关 键 词：半导体器件 加速退化试验 可靠性 寿命评估 

分 类 号：TN722.7[电子电信—电路与系统]