数字电路抗单粒子瞬态效应的最小尺寸设计  

Gate Sizing to Radiation Hardened for Single-event Transients in Digital Logic

作　　者：田海燕[1] 周晓彬[1] 陈菊[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2015年第4期20-22,共3页Electronics & Packaging

摘　　要：随着体硅CMOS电路工艺的不断缩小,数字电路在空间中使用时受到的单粒子效应越发严重。特别是高频电路,单粒子瞬态效应会使电路功能完全失效。提出了一种基于电路尺寸计算的抗单粒子瞬态效应的设计方法,主要思想是通过辐射对电路造成的最坏特性,设计电路中MOS管的尺寸,使电路在系统开销和降低软错误率之间达到一个平衡。从单粒子效应电流模型入手,计算出单粒子效应在电路中产生的电荷数,得出为抵消单粒子效应产生的电荷需要多大的电容,再折算到器件电容上,最终得到器件的尺寸。此工作为以后研制抗辐射数字电路奠定了基础,提供了良好的借鉴。Digital logic technology scaling will result in greater sensitivity to the radiation effect when used in space. Single-event transients will make complete failure of circuit function, especially in high frequency circuit. A W/L design radiation hardening technique for cost effective reduction of failure in digital logic is described. The key idea is to exploit worst case characteristics of circuit, then design the W/L of MOS to achieve cost effective tradeoffs between overhead and soft error failure. This work starts with current model of single-event effect, figures out the charge in circuit which single-event effect produce, then obtains the capacitance for offsetting those charge, converts to MOS device parasitic capacitance, works out the MOS W/L which we need. This work supplies a good technologic base for design of radiation hardened digital logic in the future.

关 键 词：辐射效应 抗辐射加固 数字电路 单粒子瞬态效应 

分 类 号：TN303[电子电信—物理电子学]