用于后栅工艺的SOI-FinFET选择性沟道缩小技术  

Application of the Selective Channel Fin Scaling on the Gate-Last Process of the SOI-FinFET

作　　者：李俊锋[1] 马小龙[1] 王防防 许淼[1] 

机构地区：[1]中国科学院微电子研究所微电子器件与集成技术重点实验室,北京100029

出　　处：《微纳电子技术》2015年第7期460-473,共14页Micronanoelectronic Technology

摘　　要：在FinFET技术中Fin的宽度对器件性能有重要影响。较窄的Fin能够更好地抑制短沟道效应,改善器件亚阈值特性,但同时也导致源漏扩展区寄生电阻增大,驱动电流减小。提出了一种用于FinFET后栅工艺的选择性沟道缩小技术,即在去除多晶硅假栅后,对沟道区露出的Fin进行氢气(含氯基)热退火处理,在减小沟道区Fin的宽度、使沟道区Fin表面光滑的同时,保持源漏扩展区Fin的宽度不变。这种自对准的沟道缩小方法简单有效地解决了亚阈值特性和源漏扩展区寄生电阻对Fin宽要求不一致的问题,并改善了器件的拐角效应。这项工艺集成技术应用于栅长为25 nm^0.5μm的SOI-FinFET器件结构中,并测试得到了良好的器件电学特性。The Fin width has an important influence on the device performances in FinFET technology.The narrower Fin can better suppress the short channel effect and improve the subthreshold characteristic of the device,but in the meantime,increase the source/drain extension parasitic resistance and decrease the driven current.A selective channel Fin scaling technology was presented for the gate-last FinFET device.The channel Fin was processed by hydrogen thermal annealing with chloride after removing poly-Si dummy gate.The method can reduce the width of channel Fin,smooth the surface of the channel Fin and keep the width of source/drain extension Fin unchangeable at the same time.The self aligned selective channel Fin scaling solves the contradiction of different Fin width requirements for subthreshold characteristic and source/drain extension parasitic resistance,and improves the corner effect of the device.The process integration technology was applied to the SOI-FinFET device with the gate length of 25 nm-0.5μm.The test shows that the electrical characteristic of the device is good.

关 键 词：FinFET器件 SOI衬底 后栅工艺 选择性沟道缩小 亚阈值特性 

分 类 号：TN385[电子电信—物理电子学]