并行可配置浮点矩阵乘法IP核设计  

A Parallel Configurable Floating- point Matrix Multiplier IP Core Design

作　　者：乔瑞秀[1] 鲁华祥[1] 龚国良[1] 陈刚[1] 

机构地区：[1]中国科学院半导体研究所高速电路与神经网络实验室,北京100083

出　　处：《网络新媒体技术》2015年第6期31-36,共6页Network New Media Technology

基　　金：国家自然科学基金(No.61401423)资助;中国科学院战略性先导专项基金项目(XDA06020700)资助

摘　　要：矩阵乘法是信息处理领域的常见计算,该文设计并实现了一个可自由配置的浮点矩阵乘法IP核,可满足不同计算场合的需求。该IP核采用并行结构设计,使用AXI接口,可通过参数配置实现任意维矩阵乘法,并在嵌入式系统设计中灵活调用,在Xilinx 7系列芯片的FPGA平台上进行验证了。实验结果证明了该浮点矩阵乘法IP核相对于传统乘法器设计具有计算速度快、移植性能好、资源利用少等特点。Matrix multiplication is frequently used in the field of information processing. A configurable floating- point matrix multiplier IP core is proposed and implemented in this paper to meet different calculation requirements. This IP core is designed in parallel structure with AXI protocol. It can realize arbitrary dimension matrix multiplication through the configuration of parameters and suits well in the embedded system design. The IP core is verified on the Xilinx 7- Series FPGA platform. The experimental results showed that compared with traditional matrix multiplications,the floating- point matrix multiplier IP core design have many advantages,such as high computing speed,great portability,and less resource utilization.

关 键 词：系统设计 IP核 浮点数运算 矩阵乘法 

分 类 号：TN791[电子电信—电路与系统]