基于0.35μm CMOS工艺的APD器件仿真分析  

Simulation of APD Device Based on 0.35μm CMOS Process

作　　者：王巍[1] 杜超雨 王婷[1] 鲍孝圆 陈丽[1] 王冠宇[1] 王振[1] 黄义[1] 

机构地区：[1]重庆邮电大学光电工程学院/国际半导体学院,重庆400065

出　　处：《半导体光电》2015年第6期888-891,908,共5页Semiconductor Optoelectronics

摘　　要：提出了一种基于0.35μm CMOS工艺的、具有p^+/n阱二极管结构的雪崩光电二极管(APD),器件引入了p阱保护环结构。采用silvaco软件对CMOS-APD器件的关键性能指标进行了仿真分析。仿真结果表明:p阱保护环的应用,明显降低了击穿电压下pn结边缘电场强度,避免了器件的提前击穿。CMOS APD器件的击穿电压为9.2V,工作电压下响应率为0.65A/W,最大内部量子效率达到90%以上,响应速度能够达到6.3GHz,在400~900nm波长范围内,能够得到很大的响应度。An avalanche photodiode（APD）with p^＋/n-well diode structure was proposed based on 0.35μm CMOS process,and p well guard ring（GR）was used to prevent premature breakdown.The properties of the proposed APD including the electric field intensity,the response rate,quantum efficiency and frequency characteristic were simulated and analyzed.The results show that：with p well GR,this premature edge breakdown is alleviated and sufficient avalanche gain is obtained,the avalanche breakdown voltage of CMOS APD is 9.2 V,the responsivity is 0.65A/W,the maximum internal quantum efficiency is about 90%,the detected signal bandwidth can reach 6.3GHZ,and the working wavelength is from 400～900nm.

关 键 词：0.35μm CMOS工艺 雪崩光电二极管 器件仿真 边缘击穿 保护环 

分 类 号：TN722.3[电子电信—电路与系统]