缓解电路NBTI效应的改进门替换技术  

Improved gate replacement technique for mitigating circuit NBTI effect

作　　者：朱炯[1] 易茂祥[1] 张姚[1] 胡林聪 刘小红[1] 程龙[1] 黄正峰[1] 

机构地区：[1]合肥工业大学电子科学与应用物理学院,合肥230009

出　　处：《电子测量与仪器学报》2016年第7期1029-1036,共8页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金(61371025;61274036;61574052)资助项目

摘　　要：纳米工艺水平下,负偏置温度不稳定性(negative bias temperature instability,NBTI)成为影响集成电路可靠性的关键性因素。NBTI效应会导致晶体管阈值电压增加,老化加剧,最终导致电路时序违规。为了缓解电路的NBTI效应,引入考虑门的时延关键性的权值识别关键门,通过比较关键门的不同扇入门替换后的时延增量,得到引入额外时延相对较小的双输入的需要替换的门,最后进行门替换。对基于45 nm晶体管工艺的ISCAS85基准电路实验结果显示,在电路时序余量为5%时,应用本文改进的门替换方法电路时延改善率为41.23%,而面积增加率和门替换率分别为3.17%和8.99%,明显优于传统门替换方法。Negative bias temperature instability （NBTI） is a key factor affecting the reliability of the integrated circuit at the nanometer level. The NBTI effect will cause the increase of transistor threshold voltage, prick up the aging of the circuit, and finally result in the circuit timing violations. In order to mitigate the NBTI effect of the circuit, in this paper, we identify critical gates with the weight of the gate considering the gate delay, then get the required replaced gates which introduce less additional delay through comparing the increased delay of critical gates＇ different fan-in gates, and these gates will be finally replaced. The experimental results on ISCAS85 benchmark circuits and 45 nm transistor model show that, the area increase rate and the gate replacement rate is reduced to 3.17% and 8.99% respectively while the average delay improvement is increased to 41.23% with the circuit timing margin 5%. And this result performs better than traditional gate replacement technique.

关 键 词：负偏置温度不稳定性 时序违规 时延关键性 关键门 门替换 

分 类 号：TN407[电子电信—微电子学与固体电子学]