一种适用于FPGA系统中的变速箱电路设计  

Design of Gearbox Circuits for FPGA System

作　　者：罗旸[1] 何光旭[1] 雷淑岚[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214072

出　　处：《电子与封装》2016年第10期19-22,26,共5页Electronics & Packaging

摘　　要：设计了一种新型变速箱电路,变速箱两边采用同一时钟,不需要额外的时钟输入,使用计数器来控制位宽转变的整个过程,并产生标志位来控制变速箱数据的输入和输出。在不改变数据传输波特率的情况下,解决在传输过程中数据的重复或丢失问题,实现两边不同数据位宽的正确转换。电路适用于在FPGA系统中,模块之间或者各IP之间的数据位宽不匹配的情况下调整模块之间的数据位宽,从而实现各内部模块之间的数据位宽匹配。仿真结果表明,以66位数据转64位数据为例,在不影响有效数据传输速率的情况下,可以在32个时钟周期内完成数据的无损转换。In the paper, a new design of gearbox that adapts the same clock at the both sides instead of involving an extra clock input is presented. It controls the whole process of bit width conversion by counters and produces flag bit to determine the input and output of the gearbox data. The design solves the problem of data repetition and loss during the transmission under fixed baud rate and consequently realizes the perfect conversion between the different bit-wide data. Under the situations when the data bit width are different among modules or IPs, the design is effective in adjusting and matching the data bit widths among modules.The simulation results show that the gearbox completes the data conversion from 66 bits to 64 bits within 32 clock cycles without loss of data rate.

关 键 词：变速箱 标志位控制 高速串行通信 SERDES FPGA系统 

分 类 号：TN402[电子电信—微电子学与固体电子学]