基于DDS的增量式PID闭环控制算法在FPGA中的实现  

Incremental PID Closed-loop Control Algorithm Based on DDS is Implemented in FPGA

作　　者：苗中华[1] 李晖[1] 高健[1] 郝付平[2] 

机构地区：[1]上海大学机电工程与自动化学院,上海200072 [2]中国农业机械化科学研究院,北京100083

出　　处：《工业控制计算机》2017年第8期35-36,共2页Industrial Control Computer

基　　金：国家重点研发计划项目(2016YFD0701401)

摘　　要：为了克服传统设计的不足,提出了将任意波形发生和对波形实现PID控制在单片FPGA中实现的思路,并以EP2C20Q240C8N芯片为SOPC系统的载体,完成系统硬件平台搭建。最后,对实验结果进行了仿真与分析,验证了方案的可行性,对单片可编程逻辑器件FPGA在该控制领域中的应用具有指导意义。In order to overcome the shortcomings of traditional design,this paper proposes a new implementation way of the realization of arbitrary waveform and the algorithm of PID control in single chip FPGA.And by choosing the EP2C20Q240C8N chip as the carrier of SOPC system,complete system hardware platform.Finally,the experimental results of the simulation and analysis validates the feasibility of the scheme,and has guiding significance for application in the relevant field of the control.

关 键 词：FPGA 增量式PID VERILOG HDL DDS技术 

分 类 号：TN791[电子电信—电路与系统] TP273[自动化与计算机技术—检测技术与自动化装置]