一种MCU可测性优化设计  

The Optimal Design for Testability on MCU

作　　者：范学仕 刘云晶 FAN Xueshi;LIU Yunjing(China Key System Co,Ltd,Wuxi 214072,China)

机构地区：[1]中科芯集成电路股份有限公司,江苏无锡214072

出　　处：《电子与封装》2018年第8期28-32,共5页Electronics & Packaging

摘　　要：为了降低测试成本,提高测试效率,将测试资源划分技术和测试端口复用技术相结合,基于ATE外部测试和BIST内部测试的优点,进行可测性设计。基于ATE的外部测试方法,设计了数字逻辑SCAN链和模拟IP测试模式。基于BIST内部测试方法,设计了MBIST电路,对Memory进行测试。为更高效地下载程序和功能验证,设计了支持标准SPI协议的通用测试接口;同时设计了测试模式管理模块,对整个可测性设计进行优化,可实现多个IP同时测试,并在实际芯片中得到验证。Based on the advantages of ATE external test and MBIST internal test,a DFT design methods combined the test resource partition(TRP)technologyand port reuse technology,was presented in this paper for the sake of reducing test cost and improving test efficiency.The SCAN chains of digital logical and test modes of analog IPs were designed based on ATE external test.What's more,the MBIST circuit for memory testing was devised based on MBIST internal test.Besides,a universal testing interface supporting standard SPI protocol was designed to enhance efficiency of testing and downloading.In order to optimize the whole design,a management module of test modes was proposed,which actualized the testing for multi-IPs at the same time.The proposed DFThas been implemented in an actual wafer.

关 键 词：MCU 可测性设计 资源划分技术 MBIST 

分 类 号：TN402[电子电信—微电子学与固体电子学]