ZYNQ的卷积神经网络硬件加速通用平台设计  

Design of Hardware Acceleration General Platform for CNN Based on ZYNQ

作　　者：冯光顺 应三丛[1] Feng Guangshun;Ying Sancong(School of Computer Science,Sichuan University,Chengdu 610065,China)

机构地区：[1]四川大学计算机学院,成都610065

出　　处：《单片机与嵌入式系统应用》2019年第3期3-6,9,共5页Microcontrollers & Embedded Systems

基　　金：四川省科技厅科技支持项目(2016GZ0097)

摘　　要：近年来卷积神经网络(CNN)在人工智能领域备受关注,被越来越多应用到实际生产中。为了较好地实现工程应用,需要将算法固化到嵌入式平台上。由于卷积神经网络的数据计算并行度高、计算量大,现场可编程门阵列成为对其进行硬件加速的重要工具。本文基于Xilinx ZYNQ ZC706设计实现了卷积神经网络硬件加速的通用平台,可以满足不同卷积神经网络算法模块实现硬件加速的需求。Convolutional Neural Network is attracted more attention recently in AI field,more and more applications are used in industry field using it.In order to enhance the application value,it is meanful to implement algorithms on embedded systems.Due to the large computing quantity and high degree of parallelism,FPGA has become a conspicuous tool as a hardware accelerator of algorithms.In this paper,a novel hardware platform is designed to accelerate CNN algorithms by Verilog HDL on Xilinx ZYNQ ZC706 board,which meets the needs of different kinds of implementation of CNN design modules.

关 键 词：ZC706 卷积神经网络 硬件加速 FPGA ZYNQ 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]