基于现场可编程门电路的人脸检测识别加速平台  

Acceleration platform for face detection and recognition based on field-programmable gate array

作　　者：周柚[1,2] 杨森 李大琳 吴春国[1,2] 王岩[1,2] 王康平[1,2] ZHOU You;YANG Sen;LI Da-lin;WU Chun-guo;WANG Yan;WANG Kang-ping(College of Computer Science and Technology,Jilin University,Changchun 130012,China;Key Laboratory of Symbol Computation and Knowledge Engineering of Ministry of Education,Jilin University,Changchun 130012,China)

机构地区：[1]吉林大学计算机科学与技术学院,长春130012 [2]吉林大学符号计算与知识工程教育部重点实验室,长春130012

出　　处：《吉林大学学报（工学版）》2019年第6期2051-2057,共7页Journal of Jilin University:Engineering and Technology Edition

基　　金：国家自然科学基金项目（61772227）;吉林省科技发展计划重点研发项目（20180201045GX,20160101259JC）;吉林省大数据智能计算重点实验室项目（20180622002JC）

摘　　要：采用现场可编程门电路(FPGA)和中央处理器相结合的异构计算技术,解决人脸检测和识别计算加速问题。基于并发和流水线的方法加速Viola-Jones人脸检测算法,提高了数据吞吐量,增加了级联分类器的并行度;通过并发卷积操作和流水线特征图加速了卷积神经网络计算过程。实验结果表明,硬件平台较软件平台实现了2.9倍的加速比。A heterogeneous computing technique based on Field-Programmable Gate Array(FPGA)is proposed in this paper.The Viola-Jones face detection algorithm is accelerated based on concurrent and pipelining methods to improve data throughput and increase the parallelism of cascaded classifiers and convolution neural network is accelerated by concurrent convolution and pipelined feature maps.The experimental results show that the hardware platform achieves a speedup of 2.9 times compared with the software platform.

关 键 词：计算机应用 人脸检测 人脸识别 卷积神经网络 现场可编程门电路算法 算法硬件 

分 类 号：TP338[自动化与计算机技术—计算机系统结构]