一种基于FPGA的Viterbi译码器的研究与设计  

Research and Design of Viterbi Decoder Based on FPGA

作　　者：虞亚君 桑坤 赵参 YU Yajun;SANG Kun;ZHAO Can(China Key System&Integrated Circuit Co.,Ltd.,Wuxi 214072,China)

机构地区：[1]中科芯集成电路有限公司

出　　处：《电子与封装》2020年第1期24-27,共4页Electronics & Packaging

摘　　要：针对通信系统中传统维特比(Viterbi)译码器结构复杂、译码延时大、资源消耗大的问题,提出了一种新的基于FPGA的Viterbi译码器设计。结合(2,1,7)卷积编码器和Viterbi译码器的工作原理,设计出译码器的核心组成模块,具体采用3比特软判决译码,用曼哈顿距离计算分支度量,32个碟型加比选子单元并行运算,完成幸存路径和幸存信息的计算。幸存路径管理模块采用Viterbi截短译码算法,回溯操作分成写数据、回溯读和译码读,以改进的流水线进行并行译码操作,译码延时和储存空间分别降低至和。To solve the problems of traditional Viterbi decoder such as complicated structure,large decoding delay and high resource consumption in the communication system,a new Viterbi decoder design based on FPGA is proposed.In combination with the working principle of(2,1,7)convolutional encoder and Viterbi decoder,the core components of Viterbi decoder are designed in detail.3-bit soft-decision decoding is adopted specifically,the branch metric is calculated by using the Manhattan distance,32 butterfly-type add-compare-select subunits are operated side-by-side,and the calculation of survival path and survival information is completed.Viterbi truncated decoding algorithm is used in the module of survival path management,and backtracking operations are divided into data write,backtracking read and decoding read.Decoding operation is performed with improved pipelining concurrently so that decoding delay and storage space are reduced to and respectively.

关 键 词：VITERBI译码 卷积编码 分支度量 加比选 FPGA 

分 类 号：TN914[电子电信—通信与信息系统]