Key Process Approach Recommendation for 5 nm Logic Process Flow with EUV Photolithography  

作　　者：Yushu Yang Yanli Li Qiang Wu Jianjun Zhu Shoumian Chen 

机构地区：[1]Shanghai ICR&D Center,497 Gaosi Road,Zhangjiang Hi-Tech Park,Shanghai,China,201210

出　　处：《Journal of Microelectronic Manufacturing》2020年第1期17-22,共6页微电子制造学报（英文）

基　　金：I thank the higher management team from Shanghai IC R&D Company for the support of this work.

摘　　要：5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries.In a typical 5 nm logic process,the Fin pitch is 22~27 nm,the contact-poly pitch(CPP)is 48?55 nm,and the minimum metal pitch(MPP)is around 30~36 nm.Due to the fact that these pitches are much smaller than the resolution capability of 193 nm immersion lithography,it is also the first generation which adopts EUV photolithography technology on a large-scale where the process flow can be simplified by single exposure method from more than 10 layers.Relentless scaling brings big challenges to process integration and pushes each process module to the physical and material limit.Therefore,the success of process development will largely depend on careful balance the pros and cons to achieve both performance and yield targets.In the paper,we discussed the advantages and disadvantages of different process approaches for key process loops for 5 nm logic process flow,including dummy poly cut versus metal gate cut approaches in the metal gate loops,self-aligned contact(SAC)versus brutally aligned contact(BAC)approaches,and also introduced the self-aligned double patterning approach in the lower metal processes.Based on the above evaluation,we will provide a recommendation for module's process development.

关 键 词：5nm LOGIC Process EUV metal gate cut SAC BAC SELF-ALIGNED LELE 

分 类 号：G63[文化科学—教育学]