FPGA的可配置卷积运算单元的设计与实现  

Design and Implementation of Configurable Convolution Operation Unit Based on FPGA

作　　者：左国渭 应三丛[1] Zuo Guowei;Ying Sancong(School of Computer Science,Sichuan University,Chengdu 610065,China)

机构地区：[1]四川大学计算机学院,成都610065

出　　处：《单片机与嵌入式系统应用》2020年第11期54-58,共5页Microcontrollers & Embedded Systems

基　　金：四川省重大科技专项课题(No.2018GZDZX0024)。

摘　　要：提出了一种新的可配置卷积运算单元结构设计。该结构通过配置寄存器的信息实现重新配置卷积运算单元的电路结构,达到卷积运算单元电路复用的目的。本文以该结构为基础,设计并实现了卷积运算单元电路。对于ResNet-50网络模型,两张图片同时加速处理的时钟周期数比两张图片依次加速处理的时间周期数减少了10.26%;对于ResNet-101网络模型,两张图片同时加速处理的时钟周期数比两张图片依次加速处理的时间周期数减少了9.95%。In the paper,a new structure design of configurable convolutional unit is designed.The proposed structure can reconfigure the circuit structure of the convolutional unit by configuring the information of the relevant control registers,to achieve the purpose of circuit multiplexing of convolution operation units.Based on this structure,a circuit of convolutional operation has been designed and implemented.Finally,for the ResNet-50,the number of clock cycles in which two pictures are simultaneously accelerated is reduced by 10.26%compared to the number of clock cycles in which two pictures are sequentially accelerated.For the ResNet-101,the number of clock cycles in which two pictures are simultaneously accelerated is reduced by 9.95%compared to the number of clock cycles in which two pictures are sequentially accelerated.

关 键 词：卷积神经网络 电路复用 卷积核 可配置 

分 类 号：TP333.5[自动化与计算机技术—计算机系统结构]