一种基于ATE的SerDes物理层测试方法  

Test Method of SerDes Physical Layer Based on ATE

作　　者：张凯虹 季伟伟 朱江 ZHANG Kaihong;JI Weiwei;ZHU Jiang(China Key System&Integrated Circuit Co.,Ltd.,Wuxi 214035,China)

机构地区：[1]中科芯集成电路有限公司,江苏无锡214035

出　　处：《电子与封装》2020年第11期30-33,共4页Electronics & Packaging

基　　金：大规模集成电路高速串行接口测试方法标准研究(192ZX11012)。

摘　　要：串行传输技术特别是串行解串器(SerDes)能提供比并行传输技术更高的带宽,被广泛应用于嵌入式高速传输领域。SerDes物理层的测试需要设备的带宽大于信号速率,测试指标高且测试端口接入会对信号产生影响。大多数厂商采用仪器仪表与评估板来评估待测器件(DUT)的方式效率低下,只适用于产品评估阶段。基于自动测试设备(ATE)与可测性设计(DFT)相结合的方式,采用高速串行接口源同步测试技术、测试通路校准与补偿等技术,对SerDes产品的功能、发送和接收端参数进行全面的测试,实现高速接口的快速准确测试,并可适用于其他同类SerDes芯片测试。Serial transmission technology,especially serializer and deserializer(SerDes),which can provide higher bandwidth than parallel transmission technology,is widely used in the field of embedded high-speed transmission.In view of the bandwidth of the test equipment required for the SerDes physical layer test is larger than the signal rate,and the test index is high and the access of the test port will affect the signal,while most manufacturers use the instrument and evaluation board to evaluate the device under test(DUT),which is inefficient and only applicable to the problem of the evaluation stage.This paper is based on auto test equipment(ATE)and design for test(DFT),by using the key technologies such as source synchronous test technology of high-speed serial interface,calibration and compensation of test path,and also comprehensively tests the functions,sending and receiving parameters of SerDes products,so as to realize fast and accurate test of high-speed interface.In addition,it can be applied to other similar SerDes chip tests.

关 键 词：串行解串器 自动测试设备 可测性设计 源同步 

分 类 号：TN407[电子电信—微电子学与固体电子学]