基于FPGA的YOLOv2加速器设计  

Design of YOLOv2 Accelerator Based on FPGA

作　　者：梁洪卫[1] 白鹏程 陈建玲 孙勤江 陈明虎 薛祥凯 LIANG Hongwei;BAI Pengcheng;CHEN Jianling;SUN Qinjiang;CHEN Minghu;XUE Xiangkai(School of Electrical Engineering and Information,Northeast Petroleum University,Daqing 163318,China;Tianjin Branch,CNOOC China Limited,Tianjin 300459,China)

机构地区：[1]东北石油大学电气信息工程学院,黑龙江大庆163318 [2]中海石油(中国)有限公司天津分公司,天津300459

出　　处：《吉林大学学报（信息科学版）》2021年第4期445-450,共6页Journal of Jilin University（Information Science Edition）

基　　金：东北石油大学国家基金培育基金资助项目(2018GPYB-03)。

摘　　要：卷积神经网络(CNN:Convolutional Neural Network)计算量较大,为达到快速处理数据的目的,需借助硬件手段进行加速。因此,利用现场可编程门阵列(FPGA:Field Programmable Gate Array)并行计算的架构特性,提出了基于FPGA的并行计算加速策略。该策略采用的具体方法包括:合理分布片上内存与片下存储,降低数据读取延迟;采用多通道并行流水结构加速卷积操作;通过卷积层数据共享减少访存延迟。利用PYNQ-z2开发平台加速卷积神经网络YOLOv2,最终实现目标物体的检测识别,该设计的处理能力为27.03 GOP/s(Giga Operations Per Second,10亿次运算/s),与CPU(E5-2620V4)相比,处理能力是CPU的6.57倍,功耗是CPU的3%。CNN(Convolutional Neural Network)has large amount of computation,in order to achieve the purpose of fast data processing,hardware means are needed to accelerate.Based on the architecture characteristics of FPGA(Field Programmable Gate Array),a parallel computing acceleration strategy based on FPGA is proposed.The specific methods of this strategy include:reducing the data reading delay by reasonably distributing on-chip memory and off chip memory;accelerating the convolution operation by multi-channel parallel flow;reducing access delay by convolutional layer data sharing.PYNQ-Z2 development platform is used to accelerate the convolutional neural network YOLOv2 and achieve the detection and identification of the target object.The processing capacity of this design is 27.03 GOP/s,compared with CPU(E5-2620 v4),the processing capacity is 6.57 times that of CPU and the power consumption is 3%of CPU.

关 键 词：卷积神经网络 现场可编程门阵列 目标检测 硬件加速 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]