ARMv7架构的中断控制结构及实验设计  

Interrupt Control Structure and Experiment Design for ARMv7 Architecture

作　　者：章复嘉 林菲[1] ZHANG Fujia;LIN Fei(National Computer Experimental&Teaching Demonstration Center,Hangzhou Dianzi University,Hangzhou 310018,China)

机构地区：[1]杭州电子科技大学国家级计算机实验教学示范中心,杭州310018

出　　处：《实验室研究与探索》2022年第2期121-124,180,共5页Research and Exploration In Laboratory

基　　金：教育部第二批新工科研究与实践项目(E-ZYJG20200222);浙江省高等教育“十三五”第二批教学改革研究项目(jg20190160)。

摘　　要：中断实验设计是系统化教学背景下课程衔接的重要环节。针对地方高校开展系统能力人才培养的需求,基于字长32 bit的ARMv7模型机结构,设计一个硬件中断优先级控制实验。借助自制远程可交互式FPGA实验板卡实施教学,加深学生对中断知识点的理解,为学习后继操作系统和嵌入式系统原理打下基础。Aiming at the needs of teaching of developing system design ability in local universities,a hardware interrupt priority control experiment is designed based on 32-bit ARMv7 CPU architecture.With the help of the provincial virtual simulation experiment teaching project platform,the self-made remote interactive FPGA experiment boardsare used to implement the teaching.The experiment deepens the students’understanding of interruption knowledge,and lays the foundation for learning the design of operating system and embedded system.Interruption experiment design is an important link of course linkage under the background of systematic teaching.

关 键 词：ARMv7模型机 中断实验 课程衔接 系统能力培养 

分 类 号：G642.3[文化科学—高等教育学] TP302.2[文化科学—教育学]