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作 者:高明阳 顾钊源 杨明超 谭在超 韩传余 刘卫华[1] 耿莉[1] 郝跃[3] GAO Mingyang;GU Zhaoyuan;YANG Mingchao;TAN Zaichao;HAN Chuanyu;LIU Weihua;GENG Li;HAO Yue(School of Microelectronics,Xi’an Jiaotong University,Xi’an 710049,China;Suzhou Convert Semiconductor Co.,Zhangjiagang 215600,China;School of Microelectronics,Xidian University,Xi’an 710071,China)
机构地区:[1]西安交通大学微电子学院,陕西西安710049 [2]苏州锴威特半导体股份有限公司,江苏张家港215600 [3]西安电子科技大学微电子学院,陕西西安710071
出 处:《微电子学与计算机》2022年第7期94-100,共7页Microelectronics & Computer
基 金:国家自然科学基金项目(61771384)。
摘 要:为了实现能源的高效利用,通过减小器件的导通电阻和栅漏电容来降低MOSFET的功耗一直是功率电子学的研究热点,但二者存在折衷关系.碳化硅的材料优势使碳化硅MOSFET更适合高频应用,在不过多增大导通电阻的情况下,减小栅漏电容以降低器件在高频应用中的动态功耗是本文的设计重点.提出了一种带有沟槽型源端和N型包裹区的碳化硅沟槽MOSFET结构,被称为槽源N包裹型(Trench Source With N-type,TSN)器件,通过将栅漏电容转换为栅源和漏源电容串联的形式,在维持MOSFET的导通电阻不过多增大的前提下,降低了栅漏电容.介绍了TSN碳化硅沟槽MOSFET器件结构和制备工艺流程,通过TCAD仿真对栅沟槽深度、N型包裹区的掺杂浓度和宽度、P+型埋层的垂直注入和横向注入深度、源极槽深度进行了优化设计.仿真结果表明,器件的击穿电压达到1420 V,特征导通电阻为3.1mΩ·cm^(2),特征栅漏电容为12.4pF·cm^(-2)。在与常规UMOS结构近似相等的击穿电压下,虽然特征导通电阻略有增大,但特征栅漏电容明显降低,这两项参数的乘积降低了78.9%.In order to achieve efficient utilization of energy,lowering the power consumption of MOSFET by reducing the on-resistance and gate-drain capacitance of the device has always been a research focus of power electronics,but these two parameters have to trade off.The material advantages of silicon carbide make silicon carbide MOSFET more suitable for high frequency applications.The key point of this paper aims at reducing the gate-drain capacitance to lower the dynamic power consumption in high frequency applications without increasing the on-resistance too much.A silicon carbide trench MOSFET structure with trench source and N-type wrapped region is presented,which is called the Trench Source with N-type(TSN)device.By converting the gate-drain capacitance into the form of gate-source and drain-source capacitance series,the gate-drain capacitance is reduced on the premise that the on-resistance of MOSFET does not increase too much.Then the device structure and manufacturing process of the TSN MOSFET are introduced.The depth of gate groove,the doping concentration and width of N-type wrapped region,the vertical injection depth and horizontal injection depth of P+-type buried layer,and the depth of source groove are optimized by TCAD simulation.The simulation results show that the breakdown voltage of TSN structure is 1420 V,the specific on-resistance is 3.121 mΩ·cm^(2) and a specific gate-drain capacitance of 12.4 pF·cm^(-2) is achieved.At approximately the same breakdown voltage of the conventional UMOS structure,although the specific on-resistance of the proposed device increases slightly,the specific gate-drain capacitance decreases significantly.The product of these two parameters is decreased by 78.9%.
分 类 号:TN386[电子电信—物理电子学]
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