基于FPGA的DDR3 SDRAM控制器设计  

Design of DDR3 controller based on FPGA

作　　者：黄姣英[1] 赵如豪 王琪 高成[1] HUANG Jiaoying;ZHAO Ruhao;WANG Qi;GAO Cheng(School of Reliability and System Engineering,Beijing University of Aeronautics and Astronautics,Beijing 100191,China;The Fourth Electronic Research Institute of the Ministry of Industry and Information Technology,Beijing 100037,China)

机构地区：[1]北京航空航天大学可靠性与系统工程学院,北京100191 [2]工业和信息化部电子第四研究院,北京100037

出　　处：《现代电子技术》2022年第22期68-74,共7页Modern Electronics Technique

摘　　要：存储器控制器技术研究对于大幅降低处理器访问存储器带来的时间延迟、缓解“存储墙”问题有着十分重要的意义,常规的依赖MIG IP核设计的存储器控制器难以进行访存延迟的测试。文中选取MT41K128M16JT型号DDR3 SDRAM,基于FPGA设计DDR3 SDRAM控制器的控制模块。首先研究DDR3 SDRAM的工作原理及状态转换图;接着将控制模块划分为初始化模块、刷新模块、状态产生模块、状态控制模块四部分,使用Verilog语言进行RTL级代码实现,找到关键的时序延迟接口;最后在ModelSim中完成DDR3 SDRAM控制器控制模块的仿真。仿真结果表明,初始化、刷新等模块的输出波形满足设计的时序要求,写入的数据与读出的数据一致,可有效实现对DDR3 SDRAM初始化、刷新、写、读功能的控制。DDR3 SDRAM控制器底层代码的编写为访存延迟的测试提供了可能。The research of memory controller technology is of great significance for greatly reducing the time delay caused by the processor to access the memory and alleviating the“Memory Wall”problem.It is difficult for the conventional memory controller designed according to the MIG IP core to test the memory access delay.The MT41K128M16JT model DDR3 SDRAM is selected,and the control module of the DDR3 SDRAM controller is designed based on FPGA.The working principle and state transition diagram of DDR3 SDRAM are studied,and then the control module are divided into four parts:initialization module,refresh module,state generation module,and state control module.The Verilog language is used to achieve RTL-level code implementation,the key timing delay interface is found,and the simulation of control module of the DDR3 SDRAM controller are completed in Modelsim.The simulation results show that the output waveforms of the initialization,refresh and other modules can meet the design timing requirements,and the written data is consistent with the read data,which effectively realizes the control of the DDR3 SDRAM initialization,refresh,write,and read functions.The programming of the underlying code of the DDR3 SDRAM controller makes it possible to test the memory access delay.

关 键 词：控制器设计 DDR3 SDRAM 访存延迟 仿真测试 FPGA Verilog HDL 

分 类 号：TN791-34[电子电信—电路与系统] TP333[自动化与计算机技术—计算机系统结构]