180 nm嵌入式闪存工艺中高压NMOS器件工艺加固技术  

Radiation hardening by process technology for high voltage nMOSFET in 180 nm embeded flash process

作　　者：陈晓亮 孙伟锋 Chen Xiao-Liang;Sun Wei-Feng(National Application Specific Integrated Circuit System Engineering Research Center,School of Electronic Science&Engineering,Southeast University,Nanjing 211189,China)

机构地区：[1]东南大学电子科学与工程学院,国家专用集成电路系统工程技术研究中心,南京211189

出　　处：《物理学报》2022年第23期347-354,共8页Acta Physica Sinica

摘　　要：抗辐射嵌入式闪存工艺在航空航天领域应用广泛,其中高压NMOS器件对总剂量辐射效应最敏感,对该器件进行加固是提高芯片抗辐射能力的关键之一.本文采用浅槽隔离(STI)场区离子注入工艺对180 nm嵌入式闪存工艺中的高压NMOS器件进行加固,实验结果表明该加固器件存在两个主要问题:1)浅槽刻蚀后进行离子注入,后续热工艺较多,存在显著的杂质再分布效应,导致STI侧壁离子浓度降低,经过1×10^(5) rad(1 rad=10^(-2) Gy)(Si)辐照后,器件因漏电流增大而无法关断;2)加固离子注入降低了漏区PN结击穿电压,不能满足实际应用需求.为解决上述问题,本文提出了一种新型部分沟道离子注入加固方案.该方案调整加固离子注入工艺至热预算较多的栅氧工艺之后,减弱了离子再分布效应.另外,仅在STI边缘的沟道中部进行离子注入,不影响漏击穿电压.采用本方案对高压NMOS器件进行总剂量工艺加固,不改变器件的条形栅设计,对器件电学参数影响较小,与通用工艺兼容性好.测试结果表明,器件经过1.5×10^(5) rad(Si)总剂量辐照后,关态漏电流保持在10^(-12)A左右,这比传统的STI场区离子注入加固方案降低了5个数量级.Radiation-hardened embedded flash technology is widely used in aerospace field.The high voltage nMOSFET is the key device to be hardened as it is the most sensitive device to total ionizing dose(TID)effect.In this study,the shallow tench isolation(STI)sidewall implantation method is used to harden 5 V nMOSFET for 180 nm eFlash process.Through the study of the TID response of the device,two problems emerge in this hardening technology.Firstly,the hardening ions are implanted after STI trench etching,the doping profile is influenced by the following thermal process,resulting in lower doping concentration at STI edge.The device fails to work due to high leakage current after 1×10^(5) rad(1 rad=10^(-2) Gy)(Si)radiation.Secondly,the hardening ions that are implanted in drain region reduce the breakdown voltage of PN junction on the drain side.Device cannot satisfy the actual requirement in the circuit.To solve these problems,we propose a new device hardening method called partial channel ion implantation.Comparing with previous method,in order to reduce the doping redistribution effect,we adjust the hardening ion implantation to an extent after the oxidation of gate oxide.Moreover,an extra mask is introduced to determine the hardening implantation region to avoid ion implantation on the drain side of the device.Therefore,the drain breakdown voltage will not be influenced by hardening implantation.By using this new hardening technology for high voltage NMOS,the device can maintain the typical design of strip-type gate.The hardening method is compatible with general process technology and does not influence the electrical parameters of the device obviously.The results show that with the partial channel ion implantation method,the drain leakage of the device is kept at a pico-ampere level after 1.5×10^(5) rad(Si)radiation.That is five orders of magnitude lower than that obtained by using previous STI implantation hardening technology.

关 键 词：总剂量辐射效应 工艺加固 高压器件 嵌入式闪存 

分 类 号：TN40[电子电信—微电子学与固体电子学] TP368.1[自动化与计算机技术—计算机系统结构] V443[自动化与计算机技术—计算机科学与技术]