基于FSMO的SVM训练核的设计与实现  

Design and implementation of SVM training core based on FSMO

作　　者：邓昊 冉峰[1] 郭爱英[2] DENG Hao;RAN Feng;GUO Aiying(Microelectronics Research and Development Center,Shanghai University,Shanghai 200444,China;School of microelectronics,Shanghai University,Shanghai 200444,China)

机构地区：[1]上海大学微电子研究与开发中心,上海200444 [2]上海大学微电子学院,上海200444

出　　处：《微电子学与计算机》2023年第2期136-145,共10页Microelectronics & Computer

基　　金：上海市科技委项目(19JC1412400,18JC1410402)。

摘　　要：为了解决支持向量机(Support Vector Machine,SVM)训练的复杂性与实时性,本文提出基于单循环的快速序列最小优化算法(Fast Sequential Minimal Optimization,FSMO)来构建新的SVM训练模型.首先,针对传统序列最小优化算法(Sequential Minimal Optimization,SMO)中待优化乘子选择繁复问题,提出了轮询加随机的优选方法并设计了单循环迭代的FSMO训练架构,降低算法复杂度.其次,采用集中计算体系结构分模块设计了新的SVM训练IP核.并且将该SVM训练IP核移植到FPGA平台上进行了验证与分析.结果表明,相较于传统SMO的训练IP核,在训练准确率相似的情况下,基于FSMO的SVM训练IP核训练速度提升约39%,可节省约47%的硬件资源.In order to solve the complexity and real-time of support vector machine(SVM)training,a fast sequential minimum optimization(FSMO)algorithm based on single loop is proposed to construct a new SVM training model.Firstly,aiming at the complex selection of multipliers to be optimized in the traditional sequence minimum optimization algorithm(SMO),a polling plus random optimization method is proposed,and a single loop iterative FSMO training architecture is designed to reduce the complexity of the algorithm.Secondly,a new SVM training IP core is designed with centralized computing architecture.The SVM training IP core is transplanted to FPGA platform for verification and analysis.The results show that compared with the traditional SMO training IP core,the FSMO based SVM training IP core can improve the training speed by about 39%and save about 47%of hardware resources under the condition of similar training accuracy.

关 键 词：支持向量机 嵌入式 分解 序列最小优化 IP核 

分 类 号：TN47[电子电信—微电子学与固体电子学]