一种40 GSa/s超宽带采样保持电路  

A 40 GSa/s Ultra-wideband Track-and-hold Circuit

作　　者：罗宁 周猛 张有涛 叶庆国 LUO Ning;ZHOU Meng;ZHANG Youtao;YE Qingguo(Nanjing Guobo Electronics Co.,Ltd.,Nanjing,211100,CHN)

机构地区：[1]南京国博电子股份有限公司,南京211100

出　　处：《固体电子学研究与进展》2023年第2期163-167,共5页Research & Progress of SSE

摘　　要：基于0.7μm的InP双异质结双极晶体管(DHBT)工艺设计了一种超高速宽带采样保持电路。输入缓冲器采用Cherry-Hooper结构有效提升了电路的增益和带宽。时钟缓冲器采用多级Cascode结构提升时钟信号的带宽。芯片面积1.40 mm×0.98 mm,总功耗小于1.1 W。测试结果表明:电路可以在40 GSa/s采样速率下正常工作。电路的-3 dB带宽在采样态为24 GHz,在采样保持态为19 GHz。在采样保持态,当输入4 GHz、-6 dBm信号时,电路的总谐波失真(THD)低于-41.5 dBc,有效位数(ENOB)相当于6.6。时域测试波形在本文也有呈现。A wide bandwidth and ultra-high speed track-and-hold circuit in O.7μm InP double heterojunction bipolar transistor(DHBT)technology was presented in this paper.The gain and bandwidth of circuit were improved effectively by the Cherry-Hooper structure in input buffer.The bandwidth of clock signal was improved by multi-level Cascode structure in clock buffer.The area of the circuit is 1.4 mm×0.98 mm and the power consumption is less than 1.1 W.The experimental results show that the proposed track-and-hold circuit is capable of operating under 40 GSa/s.The-3 dB bandwidth of the circuit is 24 GHz in the sampling state and 19 GHz in the sample-and-hold state.In the sample-and-hold state,when a 4 GHz,-6 dBm signal is input,the total harmonic distortion(THD)of the circuit is lower than-41.5 dBc,ENOB is equivalent to 6.6.Time domain measurement is also presented.

关 键 词：采样保持电路 超高速 超宽带 磷化铟 异质结双极晶体管 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]