基于UVM的AHB总线SRAM控制器设计和验证  

Design and Verification of the AHB bus SRAM Controller Based on UVM

作　　者：梁光胜[1] 李朝洋 梁兆楷 杨松 LIANG Guangsheng;LI Zhaoyang;LIANG Zhaokai;YANG Song(School of Electrical and Electronic Engineering,North China Electric Power University,Beijing 102206,China)

机构地区：[1]华北电力大学电气与电子工程学院,北京102206

出　　处：《集成电路应用》2023年第6期51-53,共3页Application of IC

摘　　要：阐述AHB总线的SARM控制器运行原理和特点,以System Verilog为验证语言,VCS和DVE为仿真软件,搭建了基于UVM的通用验证平台,针对待测模块设计随机化测试用例,给出基于UVM的AHB总线SRAM控制器的验证结果,检测UVM验证平台的重用性、可移植性和可靠性。This paper describes the operation principle and characteristics of the AHB bus SARM controller,a universal verification platform based on UVM built with System Verilog as the verification language and VCS and DVE as the simulation software.Randomized test cases are designed for the modules to be tested,and the verification results of the AHB bus SRAM controller based on UVM are given to test the high reusability,portability and reliability of the UVM verification platform.

关 键 词：UVM验证方法 AHB总线 静态随机存取存储器 System Verilog VCS 

分 类 号：TN47[电子电信—微电子学与固体电子学] TP336[自动化与计算机技术—计算机系统结构]