基于3D-SiP技术的小型化混频锁相源的研制  被引量:1

Research on Miniaturized Frequency Synthesizer Based on 3D-SiP Technology

在线阅读下载全文

作  者:尹峰 钱兴成[1] 王晟[2] 潘碑[1] 陈静[1] YIN Feng;QIAN Xingcheng;WANG Sheng;PAN Bei;CHEN Jing(Nanjing Electronic Devices Institute,Nanjing,210016,CHN;The 28th Research Institute of China Electronics Technology Group Corporation,Nanjing,210007,CHN)

机构地区:[1]南京电子器件研究所,南京210016 [2]中国电子科技集团公司第二十八研究所,南京210007

出  处:《固体电子学研究与进展》2023年第3期221-226,共6页Research & Progress of SSE

摘  要:基于电路三维垂直互连,采用系统级封装技术,研制了一款Ku波段小型化锁相源,尺寸仅为16 mm×11 mm×3 mm,通过SiP模块电性能设计与电磁学、热力学、结构力学仿真的结合,实现了12~14 GHz频率信号的输出。测试结果表明,锁相源的输出信号相位噪声为-95 dBc/Hz@1 kHz,杂散抑制大于65 dBc,且测试结果与仿真结果相吻合。In this paper,according to use the technology of three-dimensional vertical interconnec-tion and system-in-package,a Ku-band frequency synthesizer was developed,which can output the frequency range of 12 GHz to 14 GHz.The overall size of this frequency synthesizer is only 16 mm×11 mm×3 mm.Moreover,this research realizes the combination of several simulations includes SiP module design,electromagnetics,thermodynamics and structural mechanics.The test results show that the phase noise of the output signal of the frequency synthesizer is-95 dBc/Hz@1 kHz,the spu-rious suppression is better than 65 dBc.Therefore,the test results of the frequency synthesizer are consistent with the simulation results.

关 键 词:三维垂直互连 系统级封装 锁相源 小型化 

分 类 号:TN45[电子电信—微电子学与固体电子学]

 

参考文献:

正在载入数据...

 

二级参考文献:

正在载入数据...

 

耦合文献:

正在载入数据...

 

引证文献:

正在载入数据...

 

二级引证文献:

正在载入数据...

 

同被引文献:

正在载入数据...

 

相关期刊文献:

正在载入数据...

相关的主题
相关的作者对象
相关的机构对象