基于UVM的可重用硬件加速器验证平台  

Verification Platform of UVM-Based Reusable Hardware Accelerator

作　　者：隋金雪[1,2] 郁添林 沈姒清 张霞 SUI Jin-xue;YU Tian-lin;Shen Si-qing;ZHANG Xia(School of Electronics and Information Engineering,Shandong Technology and Business University,Yantai Shandong 264026,China;Advanced Institute of Information Technology Peking University,Hangzhou Zhejiang 311215,China;Institute of Network Technology,Yantai Shandong 264026,China)

机构地区：[1]山东工商学院电子与信息工程学院,山东烟台264003 [2]北京大学信息技术高等研究院,浙江杭州311215 [3]中科网络技术研究所(中科院计算机所烟台分所),山东烟台264026

出　　处：《计算机仿真》2023年第8期350-354,共5页Computer Simulation

基　　金：山东省自然科学基金(2016ZRB019JQ);浙江省重点研发计划项目(2020C01SA100208)。

摘　　要：验证平台主要通过覆盖率驱动的收敛技术,并结合定向测试与可约束的随机激励,对多核加速器芯片中的IP进行功能型验证。验证环境按照卷积神经网络硬件加速器的验证需求搭建,对设计中卷积、激活、池化、全连接的功能层和基地址和数据偏移等数据流控制功能验证。实验结果证明,验证平台按照通用验证方法学(Universal Verification Methodology,UVM)中的机制,量化验证进度,确保功能模块的验证完备性;经过少量修改即可对不同结构层的神经网络模型的硬件加速器验证平台重用,缩短了验证周期。The verification platform mainly use scoverage-driven convergence technology,combined with directional testing and constrained random excitation,to perform functional verification on the IP in the multi-core accelerator chip.The verification environment was built according to the verification requirements of the convolutional neural network hardware accelerator,and the data flow control functions such as convolution,activation,pooling,and fully connected function layers in the design and the base address and data offset were verified.The experimental results prove that the verification platform quantifies the verification progress according to the mechanism in UVM to ensure the verification completeness of the functional modules;In addition,the accelerator verification platform of the network model of different structural layers can be reused with a small amount of modification,which shortens the verification cycle.

关 键 词：通用验证方法学 卷积神经网络 功能型验证 覆盖率 机制 硬件加速器 

分 类 号：TP47[自动化与计算机技术]