一种利用多P埋层的低导通电阻高压SOILDMOS结构  

A low on-resistance high-voltage SOI LDMOS structure using multiple P buried layers

作　　者：姜焱彬 李琦[1] 王磊[1] 杨保争 何智超 JIANG Yanbin;LI Qi;WANG Lei;YANG Baozheng;HE Zhichao(School of Information and Communication,Guilin University of Electronic Technology,Guilin 541004,China)

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541004

出　　处：《桂林电子科技大学学报》2023年第6期439-445,共7页Journal of Guilin University of Electronic Technology

基　　金：国家自然科学基金(61464003)。

摘　　要：为了实现低比导通电阻(Ron,sp)和高击穿电压(VBV),提出并仿真一种利用多个P埋层与阶跃掺杂漂移区的低导通电阻高电压SOI LDMOS(PL-SOI LDMOS)结构。PL-SOI LDMOS结构由多个不同的P埋层组成,其长度与浓度均在垂直方向依次递减。利用多个P埋层不仅可以增加漂移区的掺杂浓度,而且可以调制漂移区的电场,从而使Ron,sp降低和VBV提升。另外,采用阶跃掺杂漂移区的SOI LDMOS结构,阶梯掺杂分布在器件表面引起电场峰值,可调制表面电场分布。阶梯掺杂漂移区掺杂浓度从源极到漏极升高,可提高器件的VBV,同时可容纳更多的杂质原子,提供更多的电子来支持更高的电流,从而降低Ron,sp。PL-SOI LDMOS拥有较低的Ron,sp(15.8 mΩ·cm^(2))和改进的VBV(281 V)。采用Silvoca软件对结构进行设计和仿真,分析结构参数对器件性能的影响。仿真结果表明,在相同的漂移区情况下,与传统的SOI LDMOS相比,PL-SOI LDMOS的Ron,sp降低了35.8%,VBV提高55.2%。提出的结构具有较低的导通电阻和较高的VBV,器件性能得到了改善。In order to achieve low specific on-resistance(Ron,sp)and high breakdown voltage(VBV),a low on-resistance high-voltage SOI LDMOS structure using multiple P-buried layers with step doping drift region was proposed and simulated.The PL-SOI LD-MOS structure consists of several different P-buried layers with decreasing length and concentration in the vertical direction.Using multiple P-buried layers not only increases the doping concentration in the drift region,but also modulates the electric field in the drift region,resulting in Ron,sp reduction and VBV enhancement.In addition to the SOI LDMOS structure with step doping drift region,the step doping distribution causes electric field peaks on the device surface,which can modulate the surface electric field distribu-tion.The step doping drift region doping concentration rises from source to drain,can increase the breakdown voltage of the device,accommodate more impurity atoms and provide more electrons to support higher currents,thus reducing Ron,sp.PL-SOI LD-2 MOS has a reduced Ron,sp(15.8 mΩ·cm^(2))and an improved VBV(281 V).The structure was designed and simulated by Silvoca soft-ware to analyze the effect of structural parameters on device performance.In the case of the same drift region,the PL-SOI LDMOS has 35.8%lower Ron,sp and 55.2%higher VBV than the conventional SOI LDMOS.The proposed structure has lower on-resistance and higher breakdown voltage,and the structure performance is improved.

关 键 词：击穿电压 比导通电阻 多埋层 阶跃掺杂 LDMOS 

分 类 号：TN386.2[电子电信—物理电子学]