机载超轻量化卷积神经网络加速器设计  

Design of airborne ultra-lightweight convolutional neural network accelerator

作　　者：石添介 刘飞阳 张晓 SHI Tianjie;LIU Feiyang;ZHANG Xiao(Pre-research Department,AVIC Xi’an Aeronautics Computing Technique Research Institute,Xi’an 710068,China)

机构地区：[1]航空工业西安航空计算技术研究所预先研究部,西安710068

出　　处：《航空工程进展》2024年第2期188-194,共7页Advances in Aeronautical Science and Engineering

摘　　要：卷积神经网络庞大的权重参数和复杂的网络层结构,使其计算复杂度过高,所需的计算资源和存储资源也随着网络层数的增加而快速增长,难以在资源和功耗有严苛要求的机载嵌入式计算系统中部署,制约了机载嵌入式计算系统朝着高智能化发展。针对资源受限的机载嵌入式计算系统对超轻量化智能计算的需求,提出一套全流程的卷积神经网络模型优化加速方法,在对算法模型进行超轻量化处理后,通过组合加速算子搭建卷积神经网络加速器,并基于FPGA开展网络模型推理过程的功能验证。结果证明:本文搭建的加速器能够显著降低硬件资源占用率,获得良好的算法加速比,对机载嵌入式智能计算系统设计具有重要意义。The huge weight parameters and complex network layer structure of convolutional neural network make its computational complexity too high,and the required computing resources and storage resources also increase rapidly with the increase of network layers,so it is difficult to deploy in airborne embedded computing systems with strict requirements on resources and power consumption,which restricts the development of airborne embedded computing systems towards high intelligence.Aiming at the demand of ultra-lightweight intelligent computing in the resource-constrained airborne embedded computing system,a set of optimization and acceleration strategy of convolutional neural network model is proposed.After ultra-lightweight processing of the algorithm model,a con-volutional neural network accelerator is built by combining acceleration operators,and the function verification of network model reasoning process is carried out based on FPGA.The results show that the established accelerator can significantly reduce the occupancy rate of hardware resources and obtain a good algorithm speedup ratio,which is of important significance for the design of airborne embedded intelligent computing system.

关 键 词：嵌入式计算系统 卷积神经网络 轻量化 硬件加速器 FPGA验证 

分 类 号：V247[航空宇航科学与技术—飞行器设计] TP183[自动化与计算机技术—控制理论与控制工程] TP368.1[自动化与计算机技术—控制科学与工程]