无凸点混合键合三维集成技术研究进展  

Advances in Bumpless Hybrid Bonding for 3D Integration Techniques

作　　者：戚晓芸 马岩[1] 杜玉 王晨曦[1] QI Xiaoyun;MA Yan;DU Yu;WANG Chenxi(State Key Laboratory of Precision Welding&Joining of Materials and Structures,Harbin Institute of Technology,Harbin 150001,China)

机构地区：[1]哈尔滨工业大学材料结构精密焊接与连接全国重点实验室,哈尔滨150001

出　　处：《电子与封装》2024年第6期137-149,共13页Electronics & Packaging

基　　金：国家自然科学基金重大研究计划(92164105);国家自然科学基金面上项目(51975151);黑龙江省头雁团队(HITTY-20190013)。

摘　　要：数字经济时代,高密度、低延迟、多功能的芯片是推动人工智能、大模型训练、物联网等高算力需求与应用落地的基石。引线键合以及钎料凸点的倒装焊存在大寄生电容、高功耗、大尺寸等问题,使传统封装难以满足窄节距、低功耗、小尺寸的应用场景。无凸点混合键合技术能够实现极窄节距的互连,在有效避免倒装焊凸点之间桥连短路的同时降低了寄生电容,减小了封装尺寸和功耗,满足了高性能计算对高带宽、多功能的要求。对无凸点混合键合技术所采用的材料、键合工艺与方法以及当前在三维集成中的应用展开介绍,并对其发展趋势进行了展望。In the digital economy era,high-density,low-latency,and multi-functional chips are the cornerstone of high-performance computing requirements and applications such as artificial intelligence,large model training,and Internet of Things.Wire bonding and flip chip bonding with solder balls have problems such as large parasitic capacitance,high power consumption,and large size,etc.,which make traditional packaging methods difficult to meet the requirements of narrow pitch,low power consumption,and small size.The bumpless hybrid bonding technology can achieve interconnection with extremely narrow pitch,effectively avoiding short-circuiting between the bumps of flip chip bonding,reducing parasitic capacitance,package size and power consumption,and meeting the requirements of high-performance computing for high bandwidth and multi-functionality.The materials,bonding processes and methods adopted by the bumpless hybrid bonding technology,and current applications in 3D integration are introduced,and the development trend is prospected.

关 键 词：混合键合 高密度互连 三维集成 先进封装 

分 类 号：TN305.94[电子电信—物理电子学]