面向大规格矩阵协方差运算的高性能硬件加速器设计  

Design of High Performance Hardware Accelerator for Large-Scale Matrix Covariance Computation

作　　者：陈铠 刘传柱 冯建哲 滕紫珩 李世平 傅玉祥[2] 李丽[2] 何国强 CHEN Kai;LIU Chuanzhu;FENG Jianzhe;TENG Ziheng;LI Shiping;FU Yuxiang;LI Li;HE Guoqiang(Jiangsu Huachuang Microsystem Co.,Ltd.,Nanjing 211800,China;School of Electronic Science and Engineering,Nanjing University,Nanjing 210023,China)

机构地区：[1]江苏华创微系统有限公司,南京211800 [2]南京大学电子科学与工程学院,南京210023

出　　处：《电子与封装》2024年第12期64-70,共7页Electronics & Packaging

基　　金：国家自然科学基金企业创新发展联合基金重点项目(U21B2032)。

摘　　要：随着雷达系统向多通道、高带宽方向发展,大规格矩阵带来的协方差运算实时性问题限制了空时二维自适应处理(STAP)技术在先进机载雷达平台上的应用。提出了一种高性能硬件加速器设计方法,旨在满足日益增长的大规格矩阵协方差处理需求,同时提高低功耗约束下的运算效率。加速器由运算部件、控制模块、存储模块和DMA控制器组成,通过对矩阵按列分段处理的方式,在硬件存储资源有限的条件下,支持最大256×8192的矩阵协方差运算。设计了下三角运算控制逻辑,降低了运算量,并提出了一套高并发乒乓存储、流水乘累加树处理机制,提高了处理效能。流片测试结果表明,该加速器处理大规格矩阵协方差运算时性能为算力接近的CPU核的70倍以上。With the development of radar systems toward multi-channel and high bandwidth,the real-time problem of covariance operation caused by large-scale matrix limits the application of space-time adaptive processing(STAP)technology in advanced airborne radar platforms.A high performance hardware accelerator design method is proposed to meet the increasing demand for large-scale matrix covariance processing and improve computational efficiency under low-power constraints.The accelerator is composed of computing unit,control module,storage module and DMA controller.It can support up to 256×8192 matrix covariance operation under the condition of limited hardware storage resources by processing the matrix in column segments.The control logic of the lower triangulation operation is designed to reduce the amount of computation,and a high-concurrency ping-pong storage mechanism along with a pipelined multiplication-accumulation tree processing method are proposed to enhance the processing efficiency.The tape-out test results show that the performance of the hardware accelerator in large-scale matrix covariance operations is more than 70 times that of a CPU core with similar computational capabilities.

关 键 词：协方差 硬件加速器 流水计算 乘累加树 乒乓存储 

分 类 号：TN492[电子电信—微电子学与固体电子学]