基于FeFET的完全非易失全加器设计  

Fully non-volatile full adder design based on FeFETs

作　　者：王凯玥 查晓婧 王伦耀[1] 夏银水[1] WANG Kaiyue;ZHA Xiaojing;WANG Lunyao;XIA Yinshui(Faculty of Electrical Engineering and Computer Science,Ningbo University,Ningbo 315211,China)

机构地区：[1]宁波大学信息科学与工程学院,浙江宁波315211

出　　处：《宁波大学学报(理工版)》2025年第2期71-77,共7页Journal of Ningbo University:Natural Science and Engineering Edition

基　　金：国家自然科学基金(62304115,U23A20351);浙江省自然科学基金创新群体项目(LDT23F04021F04).

摘　　要：铁电场效应晶体管(Ferroelectric Field-Effect Transistor,FeFET)的滞回特性使其既可充当开关又可充当非易失性存储元件,常被应用于存内逻辑电路设计.然而现有基于FeFET的存内逻辑电路设计存在计算时需要访问部分操作数,输出需要额外的锁存器存储的问题.为此,利用FeFET构建了具有存储所有输入与输出,计算时无须访问操作数的完全非易失全加器,所设计的全加器还可以提供双轨输出信号.使用FeFET模型验证了设计功能的正确性,且与其他非易失性器件设计的全加器相比,该设计使用的器件少、延时短.The hysteresis characteristics of Ferroelectric Field-Effect Transistor(FeFET)enable it to function both as switch and non-volatile memory element,making it suitable for memory logic circuit designs.However,existing FeFET-based memory logic circuits still face the challenges such as the need to access certain operands during computation and the requirement for additional latches to store output values.In this paper,a fully non-volatile full adder is designed using FeFET,which can store all input and output values and perform computations without the need to access operands.The proposed full adder also provides dual-track output signals.The functionality of the design is validated using an FeFET model,demonstrating that it needs fewer devices and exhibits lower latency than otherwise designed with other non-volatile devices.

关 键 词：铁电场效应晶体管 存内逻辑 非易失性 全加器 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]