高性能IC版图综合中的互连线时延估计模型  

Interconnect Delay Estimation Models for Layout Synthesis of High Performance IC's

作　　者：周骥伟[1] 戎世怡[1] 刘凌志[1] 戎蒙恬[1] 

机构地区：[1]上海交通大学电子工程系,上海200030

出　　处：《微电子学》2003年第1期5-8,共4页Microelectronics

基　　金：863"高技术研究发展计划资助项目(863-SOC-Y-3-3-2)

摘　　要：　提出了一组适用于高层综合并考虑各种优化技术的互连时延估计模型,包括最优线宽设计(OWS)、缓冲插入和线宽设计(BIWS)。同Spice给出的模拟结果相比,它们能够给出准确的估计。该模型的时间的阶为一常量。因此,这些简单、快速、准确的模型可用于基于性能要求的集成电路逻辑综合和版图规划。A set of interconnect delay estimation models for highlevel synthesis is presented, which take into consideration various layout optimizations, including optimal wire sizing (OWS) and simultaneous buffer insertion and wire sizing (BIWS) All the models are shown to be accurate, compared with the results from running Spice simulations Moreover, the models run in a constant time in practiceThese simple, fast, and accurate models are applicable for performancedriven logic synthesis and floor planning

关 键 词：集成电路 互连线 时延估计 版图综合 IC版图 线宽设计 缓冲插入 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]