深亚微米工艺下互连线的串扰建模  

Crosstalk Modeling for Deep Sub-micron VLSI Interconnect

作　　者：彭嵘[1] 孙玲玲[1] 

机构地区：[1]杭州电子工业学院电子信息分院,浙江杭州310037

出　　处：《杭州电子工业学院学报》2003年第4期28-32,共5页Journal of Hangzhou Institute of Electronic Engineering

基　　金：国家863计划(90207007);浙江省自然科学基金(ZD0015)

摘　　要：深亚微米工艺下互连串扰问题成为IC设计中的"瓶颈"。在充分考虑互连线的电容耦合效应和电感耦合效应的前提下,提出了一种有效估算互连串扰噪声的方法。实验数据表明,该方法能有效估算各种工艺下的互连串扰,并能应用于不均匀互连线的情况,在效率和精度上达到了较好的折中。With the integrated circuit (IC) trending toward deep sub-micron (DSM) technology , the crosstalk problem of interconnection has become the bottle-neck in the IC design. This paper presents a new time-efficient method for the estimation of crosstalk, which considers the effect of coupling capacitances and inductors completely. Experimental result shows that the algorithm is accurate for different technology with asymmetrical interconnection and is more efficient compared with SPICE.

关 键 词：深亚微米工艺 互连线 串扰 IC设计 电容耦合效应 电感耦合效应 

分 类 号：TN402[电子电信—微电子学与固体电子学]